/*! Copyright(c) 2008-2012 Shenzhen TP-LINK Technologies Co.Ltd.
 *
 *\file		Stm8s.h
 *\brief		
 *\details	
 *
 *\author	Cai Peifeng
 *\version	
 *\date		09May12
 *
 *\warning	
 *
 *\history \arg	09May12, Cai Peifeng, Create the file
 */
#ifndef __STM8S_H__
#define __STM8S_H__

#ifdef __cplusplus
extern "C" {
#endif



#include <stdbool.h>

#include "stm8s_conf.h"

/**
 * IO definitions
 *
 * define access restrictions to peripheral registers
 */
#define     __I     volatile const   /*!< defines 'read only' permissions     */
#define     __O     volatile         /*!< defines 'write only' permissions    */
#define     __IO    volatile         /*!< defines 'read / write' permissions  */


/*!< Signed integer types  */
typedef   signed char     int8_t;
typedef   signed short    int16_t;
typedef   signed long     int32_t;

/*!< Unsigned integer types  */
typedef unsigned char     uint8_t;
typedef unsigned short    uint16_t;
typedef unsigned long     uint32_t;

#define FALSE 		   0
#define TRUE           1
#define NULL		   0

#define CONST const

//typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
#define FlagStatus     bool
#define ITStatus       bool
#define BitStatus      bool
#define BitAction      bool
#define RESET          0
#define SET            1



//typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define FunctionalState    bool
#define DISABLE            0
#define ENABLE             1


#define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))


//typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#define ErrorStatus        bool
#define ERROR              0
#define SUCCESS            1


/******************************************************************************/
/*                          IP registers structures                           */
/******************************************************************************/

/**
  * @brief  General Purpose I/Os (GPIO)
  */
typedef struct GPIO_struct
{
  __IO uint8_t ODR; /*!< Output Data Register */
  __IO uint8_t IDR; /*!< Input Data Register */
  __IO uint8_t DDR; /*!< Data Direction Register */
  __IO uint8_t CR1; /*!< Configuration Register 1 */
  __IO uint8_t CR2; /*!< Configuration Register 2 */
}GPIO_TypeDef;


 /*----------------------------------------------------------------------------*/
 /**
   * @brief  Universal Synchronous Asynchronous Receiver Transmitter (UART1)
   */
 
 typedef struct UART1_struct
 {
   __IO uint8_t SR;   /*!< UART1 status register */
   __IO uint8_t DR;   /*!< UART1 data register */
   __IO uint8_t BRR1; /*!< UART1 baud rate register */
   __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
   __IO uint8_t CR1;  /*!< UART1 control register 1 */
   __IO uint8_t CR2;  /*!< UART1 control register 2 */
   __IO uint8_t CR3;  /*!< UART1 control register 3 */
   __IO uint8_t CR4;  /*!< UART1 control register 4 */
   __IO uint8_t CR5;  /*!< UART1 control register 5 */
   __IO uint8_t GTR;  /*!< UART1 guard time register */
   __IO uint8_t PSCR; /*!< UART1 prescaler register */
 }UART1_TypeDef;

 /*----------------------------------------------------------------------------*/
 /**
   * @brief  Universal Synchronous Asynchronous Receiver Transmitter (UART1)
   */
 
 typedef struct UART3_struct
 {
   __IO uint8_t SR;   /*!< UART1 status register */
   __IO uint8_t DR;   /*!< UART1 data register */
   __IO uint8_t BRR1; /*!< UART1 baud rate register */
   __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
   __IO uint8_t CR1;  /*!< UART1 control register 1 */
   __IO uint8_t CR2;  /*!< UART1 control register 2 */
   __IO uint8_t CR3;  /*!< UART1 control register 3 */
   __IO uint8_t CR4;  /*!< UART1 control register 4 */
   __IO uint8_t reserved;
   __IO uint8_t CR6;  /*!< UART1 control register 5 */   
 }UART3_TypeDef; 

/*----------------------------------------------------------------------------*/
/**
  * @brief  SPI
  */
typedef struct SPI_struct
{
	__IO uint8_t CR1;   /*!< SPI Control Register 1 (add by Cai Peifeng:2012-6-9 15:43:6)*/
	__IO uint8_t CR2;   /*!< SPI Control Register 2 (add by Cai Peifeng:2012-6-9 15:44:59)*/
	__IO uint8_t ICR;	/*!< SPI Interrupt Control Register (add by Cai Peifeng:2012-6-9 15:45:26)*/
	__IO uint8_t SR;	/*!< SPI Status Register (add by Cai Peifeng:2012-6-9 15:46:42)*/
	__IO uint8_t DR;	/*!< SPI Data Register (add by Cai Peifeng:2012-6-9 15:47:2)*/
	__IO uint8_t CRCPR;	/*!< SPI CRC Polynomial Register (add by Cai Peifeng:2012-6-9 15:47:35)*/
	__IO uint8_t RXCRCR;/*!< SPI Rx CRC Register (add by Cai Peifeng:2012-6-9 15:48:8)*/
	__IO uint8_t TXCRCR;/*!< SPI Tx CRC Register (add by Cai Peifeng:2012-6-9 15:48:32)*/
}SPI_TypeDef;

/*----------------------------------------------------------------------------*/
/**
  * @brief  Clock Controller (CLK)
  */
typedef struct CLK_struct
{
  __IO uint8_t ICKR;     /*!< Internal Clocks Control Register */
  __IO uint8_t ECKR;     /*!< External Clocks Control Register */
  uint8_t RESERVED;      /*!< Reserved byte */
  __IO uint8_t CMSR;     /*!< Clock Master Status Register */
  __IO uint8_t SWR;      /*!< Clock Master Switch Register */
  __IO uint8_t SWCR;     /*!< Switch Control Register */
  __IO uint8_t CKDIVR;   /*!< Clock Divider Register */
  __IO uint8_t PCKENR1;  /*!< Peripheral Clock Gating Register 1 */
  __IO uint8_t CSSR;     /*!< Clock Security System Register */
  __IO uint8_t CCOR;     /*!< Configurable Clock Output Register */
  __IO uint8_t PCKENR2;  /*!< Peripheral Clock Gating Register 2 */
  uint8_t RESERVED1;     /*!< Reserved byte */
  __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */
  __IO uint8_t SWIMCCR;  /*!< SWIM clock control register */
}
CLK_TypeDef;

/******************************************************************************/
/*                          Peripherals Base Address                          */
/******************************************************************************/

/** @addtogroup MAP_FILE_Base_Addresses
  * @{
  */
#define OPT_BaseAddress         0x4800
#define GPIOA_BaseAddress       0x5000
#define GPIOB_BaseAddress       0x5005
#define GPIOC_BaseAddress       0x500A
#define GPIOD_BaseAddress       0x500F
#define GPIOE_BaseAddress       0x5014
#define GPIOF_BaseAddress       0x5019
#define GPIOG_BaseAddress       0x501E
#define GPIOH_BaseAddress       0x5023
#define GPIOI_BaseAddress       0x5028
#define FLASH_BaseAddress       0x505A
#define EXTI_BaseAddress        0x50A0
#define RST_BaseAddress         0x50B3
#define CLK_BaseAddress         0x50C0
#define WWDG_BaseAddress        0x50D1
#define IWDG_BaseAddress        0x50E0
#define AWU_BaseAddress         0x50F0
#define BEEP_BaseAddress        0x50F3
#define SPI_BaseAddress         0x5200
#define I2C_BaseAddress         0x5210
#define UART1_BaseAddress       0x5230
#define UART2_BaseAddress       0x5240
#define UART3_BaseAddress       0x5240
#define TIM1_BaseAddress        0x5250
#define TIM2_BaseAddress        0x5300
#define TIM3_BaseAddress        0x5320
#define TIM4_BaseAddress        0x5340
#define TIM5_BaseAddress        0x5300
#define TIM6_BaseAddress        0x5340
#define ADC1_BaseAddress        0x53E0
#define ADC2_BaseAddress        0x5400
#define CAN_BaseAddress         0x5420
#define CFG_BaseAddress         0x7F60
#define ITC_BaseAddress         0x7F70
#define DM_BaseAddress          0x7F90



/******************************************************************************/
/*                          Peripherals declarations                          */
/******************************************************************************/

#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)

#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)

#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)

#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)

#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)

#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)

#define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress)

#define UART1 ((UART1_TypeDef *) UART1_BaseAddress)

#define UART3 ((UART3_TypeDef *) UART3_BaseAddress)

#define CLK ((CLK_TypeDef *) CLK_BaseAddress)

#define SPI ((SPI_TypeDef *) SPI_BaseAddress)


/**
  * @brief  Definition of Device on-chip RC oscillator frequencies
  */
#define HSI_VALUE   ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */
#define LSI_VALUE   ((uint32_t)128000)   /*!< Typical Value of the LSI in Hz */
#define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz*/


#ifdef __cplusplus
 }
#endif
 
#endif	/* __STM8S_H__ */
